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1

[IEEE 2017 2nd International Conference for Convergence in Technology (I2CT) - Mumbai (2017.4.7-2017.4.9)] 2017 2nd International Conference for Convergence in Technology (I2CT) - A power-delay efficient carry select adder

Katreepalli, Raghava, Meruguboina, Drona, Haniotakis, Themistoklis

Year:

2017

Language:

english

File:

PDF, 2.41 MB

english, 2017

2

[IEEE 2020 IEEE International Symposium on Circuits and Systems (ISCAS) - Sevilla (2020.10.12-2020.10.14)] 2020 IEEE International Symposium on Circuits and Systems (ISCAS) - ARIAN: A Scalable Method for Adding aRbItrAry Numbers on Modern Processors

Poulos, Konstantinos, Anagnostopoulos, Iraklis, Haniotakis, Themistoklis

Year:

2020

File:

PDF, 159 KB

2020

3

A current monitoring technique for IDDQ testing in digital integrated circuits

Matakias, Sotiris, Tsiatouhas, Yiorgos, Arapoyanni, Angela, Haniotakis, Themistoklis

Journal:

Integration, the VLSI Journal

Year:

2015

Language:

english

File:

PDF, 3.89 MB

english, 2015

4

[IEEE 2017 IEEE International Symposium on Circuits and Systems (ISCAS) - Baltimore, MD, USA (2017.5.28-2017.5.31)] 2017 IEEE International Symposium on Circuits and Systems (ISCAS) - Reducing power, area, and delay of threshold logic gates considering non-integer weights

Mozaffari, Seyed Nima, Tragoudas, Spyros, Haniotakis, Themistoklis

Year:

2017

Language:

english

File:

PDF, 221 KB

english, 2017

5

[IEEE 8th International Symposium on Quality Electronic Design (ISQED'07) - San Jose, CA, USA (2007.03.26-2007.03.28)] 8th International Symposium on Quality Electronic Design (ISQED'07) - Transistor-Level Synthesis for Low-Power Applications

Kagaris, Dimitri, Haniotakis, Themistoklis

Year:

2007

Language:

english

File:

PDF, 229 KB

english, 2007

6

[IEEE 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - Pittsburgh, PA, USA (2016.7.11-2016.7.13)] 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design

Katreepalli, Raghava, Chemanchula, Hemanth, Haniotakis, Themistoklis, Tsiatouhas, Yiorgos

Year:

2016

Language:

english

File:

PDF, 706 KB

english, 2016

7

A Generalized Approach to Implement Efficient CMOS-Based Threshold Logic Functions

Mozaffari, Seyed Nima, Tragoudas, Spyros, Haniotakis, Themistoklis

Journal:

IEEE Transactions on Circuits and Systems I: Regular Papers

Year:

2017

Language:

english

File:

PDF, 3.72 MB

english, 2017

8

[IEEE 2020 IEEE 29th North Atlantic Test Workshop (NATW) - Albany, NY, USA (2020.6.17-2020.6.24)] 2020 IEEE 29th North Atlantic Test Workshop (NATW) - A Built In Test circuit for waveform classification at high frequencies

Poulos, Konstantinos, Haniotakis, Themistoklis

Year:

2020

File:

PDF, 544 KB

2020

9

[IEEE 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) - New York City, NY, USA (2013.10.2-2013.10.4)] 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) - Low power and high speed current-mode memristor-based TLGs

Dara, Chandra Babu, Haniotakis, Themistoklis, Tragoudas, Spyros

Year:

2013

Language:

english

File:

PDF, 1.08 MB

english, 2013

10

[IEEE 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS) - Istanbul, Turkey (2016.4.12-2016.4.14)] 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS) - Identification of delay defects on embedded paths using one current sensor

Aljubouri, Wisam, Tragoudas, Spyros, Haniotakis, Themistoklis

Year:

2016

Language:

english

File:

PDF, 152 KB

english, 2016

11

[IEEE 2017 International Conference on Communication and Signal Processing (ICCSP) - CHENNAI, India (2017.4.6-2017.4.8)] 2017 International Conference on Communication and Signal Processing (ICCSP) - Power-delay-area efficient design of vedic multiplier using adaptable manchester carry chain adder

Katreepalli, Raghava, Haniotakis, Themistoklis

Year:

2017

Language:

english

File:

PDF, 1.83 MB

english, 2017

12

[IEEE 2008 9th International Symposium of Quality of Electronic Design (ISQED) - San Jose, CA, USA (2008.03.17-2008.03.19)] 9th International Symposium on Quality Electronic Design (isqed 2008) - A High-Performance Bus Architecture for Strongly Coupled Interconnects

Skoufis, Michael N., Karmarkar, Kedar, Haniotakis, Themistoklis, Tragoudas, Spyros

Year:

2008

Language:

english

File:

PDF, 465 KB

english, 2008

13

[IEEE 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) - Taormina (2018.4.9-2018.4.12)] 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) - A 1Kx32 bit WDSRAM page with rapid write access

Simopoulos, Theodoras, Haniotakis, Themistoklis, Alexiou, George Ph.

Year:

2018

Language:

english

File:

PDF, 2.85 MB

english, 2018

14

[IEEE 2011 IEEE 9th International New Circuits and Systems Conference (NEWCAS) - Bordeaux, France (2011.06.26-2011.06.29)] 2011 IEEE 9th International New Circuits and systems conference - High performance and low power dynamic circuit design

Owda, Zaher, Tsiatouhas, Yiorgos, Haniotakis, Themistoklis

Year:

2011

Language:

english

File:

PDF, 198 KB

english, 2011

15

A Design Technique for Energy Reduction in NORA CMOS Logic

Limniotis, Konstantinos, Tsiatouhas, Yiorgos, Haniotakis, Themistoklis, Arapoyanni, Angela

Journal:

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications

Year:

2006

Language:

english

File:

PDF, 786 KB

english, 2006

16

[IEEE 2014 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) - Santorini, Greece (2014.5.6-2014.5.8)] 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) - ATPG for transition faults of pipelined threshold logic circuits

Palaniswamy, Ashok kumar, Tragoudas, Spyros, Haniotakis, Themistoklis

Year:

2014

Language:

english

File:

PDF, 264 KB

english, 2014

17

[IEEE 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Boston, MA, USA (2015.7.8-2015.7.10)] Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15) - Fast march tests for defects in resistive memory

Mozaffari, Seyed Nima, Tragoudas, Spyros, Haniotakis, Themistoklis

Year:

2015

File:

PDF, 325 KB

2015

18

ATPG for Delay Defects in Current Mode Threshold Logic Circuits

Palaniswamy, Ashok Kumar, Tragoudas, Spyros, Haniotakis, Themistoklis

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2016

Language:

english

File:

PDF, 7.53 MB

english, 2016

19

Power efficient synchronous counter design

Katreepalli, Raghava, Haniotakis, Themistoklis

Journal:

Computers & Electrical Engineering

Year:

2018

Language:

english

File:

PDF, 3.87 MB

english, 2018

20

[IEEE 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE) - Lausanne, Switzerland (2017.3.27-2017.3.31)] Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 - A new method to identify threshold logic functions

Mozaffari, Seyed Nima, Tragoudas, Spyros, Haniotakis, Themistoklis

Year:

2017

Language:

english

File:

PDF, 137 KB

english, 2017

21

[IEEE 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - Bochum, Germany (2017.7.3-2017.7.5)] 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - High Speed Power Efficient Carry Select Adder Design

Katreepalli, Raghava, Haniotakis, Themistoklis

Year:

2017

Language:

english

File:

PDF, 680 KB

english, 2017

22

[IEEE 2017 IEEE North Atlantic Test Workshop (NATW) - Providence, RI, USA (2017.5.8-2017.5.10)] 2017 IEEE North Atlantic Test Workshop (NATW) - An enhanced approach to reduce test application time through limited shift operations in scan chains

Poulos, Konstantinos, Kuchi, Jayasurya, Haniotakis, Themistoklis

Year:

2017

Language:

english

File:

PDF, 665 KB

english, 2017

23

[IEEE 2017 International Conference on Communication and Signal Processing (ICCSP) - CHENNAI, India (2017.4.6-2017.4.8)] 2017 International Conference on Communication and Signal Processing (ICCSP) - Energy-efficient synchronous counter design with minimum hardware overhead

Katreepalli, Raghava, Haniotakis, Themistoklis

Year:

2017

Language:

english

File:

PDF, 2.09 MB

english, 2017

24

[IEEE 2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - Amherst, MA, USA (2012.08.19-2012.08.21)] 2012 IEEE Computer Society Annual Symposium on VLSI - Delay Analysis for an N-Input Current Mode Threshold Logic Gate

Dara, Chandra Babu, Haniotakis, Themistoklis, Tragoudas, Spyros

Year:

2012

Language:

english

File:

PDF, 334 KB

english, 2012

25

[IEEE 2010 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - Lixouri, Greece (2010.07.5-2010.07.7)] 2010 IEEE Computer Society Annual Symposium on VLSI - Memory-Less Pipeline Dynamic Circuit Design Technique

Haniotakis, Themistoklis, Owda, Zaher, Tsiatouhas, Yiorgos

Year:

2010

Language:

english

File:

PDF, 398 KB

english, 2010

26

Testable Designs of Multiple Precharged Domino Circuits

Haniotakis, Themistoklis, Tsiatouhas, Yiorgos, Nikolos, Dimitris, Efstathiou, Constantine

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2007

Language:

english

File:

PDF, 161 KB

english, 2007

27

Securing sensor networks: A novel approach that combines encoding, uncorrelation and node disjoint transmission

Khadija Stewart, Themistoklis Haniotakis, Spyros Tragoudas

Journal:

Ad Hoc Networks

Year:

2012

Language:

english

File:

PDF, 558 KB

english, 2012

28

[IEEE 8th International Symposium on Quality Electronic Design (ISQED'07) - San Jose, CA, USA (2007.03.26-2007.03.28)] 8th International Symposium on Quality Electronic Design (ISQED'07) - Glitch Control with Dynamic Receiver Threshold Adjustment

Skoufis, Michael N., Wang, Haibo, Haniotakis, Themistoklis, Tragoudas, Spyros

Year:

2007

Language:

english

File:

PDF, 186 KB

english, 2007

29

[IEEE 2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST) - Thessaloniki, Greece (2016.5.12-2016.5.14)] 2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST) - Implementation of a 256×8 Sector Size SRAM grid with memory write speedup on CeidMem library

Simopoulos, Theodoros, Haniotakis, Themistoklis, Alexiou, George Ph.

Year:

2016

Language:

english

File:

PDF, 3.06 MB

english, 2016

30

Delay Analysis for Current Mode Threshold Logic Gate Designs

Dara, Chandra Babu, Haniotakis, Themistoklis, Tragoudas, Spyros

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2016

Language:

english

File:

PDF, 2.69 MB

english, 2016

31

A Methodology for Transistor-Efficient Supergate Design

Kagaris, Dimitri, Haniotakis, Themistoklis

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2007

Language:

english

File:

PDF, 246 KB

english, 2007

32

[IEEE 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Amsterdam, Netherlands (2014.10.1-2014.10.3)] 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Diagnosis of segment delay defects with current sensing

Aljubouri, Wisam, Somashekar, Ahish Mysore, Haniotakis, Themistoklis, Tragoudas, Spyros

Year:

2014

Language:

english

File:

PDF, 204 KB

english, 2014

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